A continuous scaling (e.g., a gate length, an oxide thickness, an other device dimension, etc.) of a transistor (e.g., a MOSFET, a JFET, a HEMT, a BJT, etc.) may allow increasingly more transistors to be packed on an IC chip (e.g., a microprocessor, a memory, a RF transmitter/receiver, etc.) while occupying a smaller area and operating at a higher frequency. An increased complexity in a design, manufacturing, and fabrication process may lead to an aggravated susceptibility to defects (e.g., functional defects, timing-related defects, etc.).
A design for test (DFT) technique is a design method that may include testability hardware features on the IC chip. The design for test technique may be used with an automatic test pattern generator (ATPG) tool (e.g., SYNOPSYS Tetramax ATPG, etc.) to generate an application specific test pattern to locate the defects on the IC chip. The defects may cause the IC chip to malfunction (e.g., fail to meet a design specification, fail to operate, etc.). As a result, an efficiency (e.g., a required time for carrying out the testing, etc.) and an effectiveness (e.g., fault coverage, etc.) of a test method (e.g., stuck-at-fault testing, IDDQ testing, at-speed testing, etc.) are critical metrics that an IC company (e.g., Texas Instruments, Intel, AMD, Motorola, Infineon, IBM, etc.) may use to evaluate the design-for-test technique.
The continuous scaling of the transistor may also cause a number of the timing-related defects to drastically increase. As such, at-speed testing has become imperative for a deep-submicron (DSM) design to ensure operability of the IC chip. At-speed testing may include a path delay model which may target a cumulative delay along a circuit path as well as a transition fault model which may target a delay (e.g., a slow to rise delay and/or a slow to fall delay) at a gate output.
There may be two fault pattern generation methods for the transition fault model that may be used in a scan chain (e.g., a chain of flip-flops, a shift register, etc.); namely, a launch-off-shift (LOS) method and a launch-off-capture (LOC) method. The launch-off-shift method may be a preferred method as a shorter and simpler test pattern may be generated from an automatic test pattern generator (ATPG) due to a combinatorial nature (e.g., no memory elements, and/or no storage elements, etc.). On the other hand, the test pattern generated from the automatic test pattern generator (ATPG) for the launch-off-capture may be longer and more complicated due to a sequential nature (e.g., has memory elements, and/or storage elements, etc.). The shorter and simpler test pattern may allow for higher fault coverage as well as decreased testing time.
Thus, the IC company may benefit significantly from ubiquitous use of the launch-off-shift method for testing the IC chip. However, a major obstacle to prevalent usage of the launch-off-shift method is that a scan enable signal must be able to switch at-speed. This may be difficult to achieve as a fanout load (e.g., a combination of a scan chain, a shift register, an inverter, and/or a flip-flop, etc.) of the scan enable signal may be sizable due to an increasing design size and complexity. While a pipeline scan enabled scheme may be used to divide the fanout load of the scan enable signal, routing awareness is increased and may lead to reduced flexibility with regards to using a place-and-route (PNR) tool. The reduced flexibility when using the place-and-route tool could further complicate the design process when trying to meet a timing closure.